1. Field of the Invention
The present invention relates generally to a circuit for operating on digital data, and is more particularly directed to an operating circuit in which digital data words which are elements of a Galois field GF(2.sup.m) are multiplied or divided for encoding or decoding a BCH error correcting code or other similar code.
2. Description of the Prior Art
Many recently proposed systems for processing and recording a high fidelity audio signal first convert the audio signal to a digital signal, and then encode the digital signal as a pulse-code modulated (PCM) signal for recording. The recorded PCM signal can be picked up and converted to a high fidelity analog signal without appreciable loss of quality.
In order to eliminate annoying crackle or popping that can occur when errors accompany the reproduced PCM signal, data words of the digital signal to be recorded are first encoded for error correction, for example by a cross-interleaving technique, and error correction words are formed and accompany the cross-interleaved data words. Then, upon reproduction, any random errors can be corrected by means of syndromes formed by using the error-correction words, and any burst errors (for exammple, due to drop out) can be spread over many words by means of the cross-interleaving technique, and can be effectively corrected or masked.
Examples of such error correction techniques are disclosed, for example, in U.S. Pat. Appln. Ser. Nos. 230,395, filed Feb. 2, 1981, U.S. Pat. No. 4,398,292, and U.S. Pat. No. 4,413,340, all of which have a common assignee herewith.
In a typical such technique, a matrix-type error correction coding system is used, such as Bose-Chaudhuri-Hocquenghen (BCH) coding or Reed-Solomon (RS) coding. These error correction coding systems are generally in the class of q-nary convolutional coding systems whose outputs can be considered as combinations of elements of a Galois field GF(2.sup.m). Accordingly, special operating circuits are required for operating on the data words as elements of a Galois field.
Currently, such operating circuits are constructed as complex arrays of logic gates. These circuits are generally quite irregular in design and require a vast number of custom connections. Consequently, it is not practical to form an operating circuit as an integrated circuit (IC). Furthermore, even if such a circuit were integrated onto a semiconductor chip, the complexity of the circuit would require the surface area of the chip to be excessively large.